library verilog;
use verilog.vl_types.all;
entity processor is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        databus         : inout  vl_logic_vector(7 downto 0);
        rda             : in     vl_logic;
        tbr             : in     vl_logic;
        iocs            : out    vl_logic;
        iorw            : out    vl_logic;
        ioaddr          : out    vl_logic_vector(1 downto 0);
        dipsw           : in     vl_logic_vector(1 downto 0)
    );
end processor;
